FIG. 1 is a block diagram illustrating a conventional delay adjusting circuit. Referring to FIG. 1, the conventional delay adjusting circuit includes first to third delay parts 110 to 130 and first to fourth NAND gates 141 to 144. The first delay part (delay1) 110 has six inverters to delay an input signal signal—in from an external circuit. These six inverters are in series connected to each other and work in a normal mode. The second delay part (delay2) 120 has two inverters to delay the input signal signal—in. These two inverters are also connected in series and work in a test mode. The delay time of the second delay part 120 is different from that of the first delay part 110 because the member of inverters in the first delay part 110 is different from that in the second delay part 120. The third delay part (delay3) 130 has four inverters to delay the input signal signal—in. These four inverters are in series connected to each other and work in a test mode. The delay time of the third delay part 130 is different from that of the first and second delay parts 110 and 120 because the member of inverters in the third delay part 130 is different from that in the first and second delay parts 110 and 120, respectively. The first NAND gate 141 receives an inverted signal of a test mode signal test—mode and an output signal of the first delay part 110, thereby NANDing the inverted test mode signal and the output signal of the first delay part 110. The second NAND gate 142 receives the inverted test mode signal, an output signal of the second delay part 120 and a test selection signal test—sel, thereby NANDing the received signals. The third NAND gate 143 receives the inverted test mode signal, an inverted signal of the test selection signal test—sel and an output signal of the third delay part 130, thereby NANDing the received signals. The fourth NAND gate 144 receives output signals of the first to third NAND gates 141 to 143 to perform a NAND operation.
In a normal mode, since the test mode signal test—mode is not activated and is in a low voltage level, the NAND gate 141 receiving the inverted test mode signal produces an output signal in response to the input signal signal—in. In this normal mode, the second and third NAND gates 142 and 143 are always in a high voltage level, irrespective of the input signal signal—in. The NAND gate 144 receives high voltage level signals from the second and third NAND gates 142 and 143 and an output signal (logic low level) from the first NAND gate 141, thereby producing a delay signal which is determined by a delay time of the first delay part 110. At this time, since the normal mode is not a test mode, the test selection signal test—sel is not activated and is in a low voltage level. Further, in the test mode, the first NAND gate 141 receiving an inverted signal of the test mode signal test—mode outputs a high voltage level signal irrespective of the input signal signal—in because the test mode signal is activated and is in a high voltage level.
When a delayed signal from the second delay part 120 is required during the test mode operation, the test selection signal test—sel is activated and is in a high voltage level. In this case, the third NAND gate 143 receiving the inverted signal of the test selection signal always outputs a high voltage level signal, irrespective of the input signal signal—in. Therefore, only second NAND gate 142 produces an output signal responsive to the input signal signal—in. The fourth NAND gate 144 receives an output signal of the second NAND gate 142, which is produced by the delay signal from the second delay part 120, to receive the input signal signal—in.
On the other hand, when a delayed signal from the third delay part 130 is required during the test operation, the test selection signal test—sel is activated and is in a high voltage level. In this case, the second NAND gate 142 receiving the inverted signal of the test selection signal always outputs a high voltage level signal, irrespective of the input signal signal—in. Therefore, only third NAND gate 143 outputs an output signal responsive to the input signal signal—in. The fourth NAND gate 144 receives an output signal of the third NAND gate 143, which is produced by the delay signal from the third delay part 130, to receive the input signal signal—in.
However, since the above-mentioned delay adjusting device is limited to a few numbers of delay parts, only predetermined delay time can be achieved. As a result, the conventional delay adjusting device can not obtain different kinds of testing modes. Even if a member of delay parts and a decoding circuit can be considered in a modification circuit, each bit of the test address to select a delay part must be allocated to corresponding pins and lots of pins must be provided. Further, it is difficult to provide many numbers of pins which are sufficient to provide various delay time.